Controller board: ESP32 + 2x StepStick carrier (v0.4), FluidNC config
- KiCad project generated by pcb/tools (design, route, schematic, fab outputs). - v0.4 fixes the v0.3 review findings: low-dropout 3.3 V regulator, OR'd 5 V supply, polyfuse, USB ESD protection, input clamps, ceramic decoupling at the drivers, A4988/DRV8825 jumper, ground stitching. DRC/ERC clean. - v0.3 (as ordered) kept in pcb/archive/v0.3. - FluidNC config.yaml for the board; rho hard limit on. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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"""Place + route the SandTable controller and write the KiCad board."""
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import math
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import os
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import sys
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import time
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sys.path.insert(0, os.path.dirname(__file__))
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import design as D
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from board import build, check_placement, write_pcb, write_project, keepout_zone, text_node
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import router as R
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OUT = os.path.expanduser('~/kicad/sandtable-controller')
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# routing width per net
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WIDTH = {}
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for n in D.NETS:
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WIDTH[n] = 0.2
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for n in ('VIN_RAW', 'VIN_FUSED', '+12V'):
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WIDTH[n] = 0.8
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WIDTH['GND'] = 0.5
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for n in ('X_1A', 'X_1B', 'X_2A', 'X_2B', 'Y_1A', 'Y_1B', 'Y_2A', 'Y_2B'):
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WIDTH[n] = 0.5
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for n in ('VBUS', '+3V3'):
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WIDTH[n] = 0.4
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for n in ('+5V', '+5V_REG'): # up to 1 A from the 5 V regulator (LED strip)
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WIDTH[n] = 0.6
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FALLBACK = [0.3, 0.2]
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# nets that must keep their full width: fail loudly instead of necking down
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NO_FALLBACK = {'VIN_RAW', 'VIN_FUSED', '+12V', 'X_1A', 'X_1B', 'X_2A', 'X_2B', 'Y_1A', 'Y_1B', 'Y_2A', 'Y_2B'}
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VIA_PAD_GAP = 0.2 # min copper gap between a via and any pad (keeps holes out of solder pads)
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def radius(w):
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return round(w / 2 + R.CLEAR + R.MARGIN, 3)
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def via_radius(w):
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return max(radius(w), round(R.VIA_D / 2 + R.CLEAR + R.MARGIN, 3))
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# Hand-routed USB-C escape (pads are on a 0.5 mm pitch). Board coords.
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USB_X = 7.445
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PREROUTE = {
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'USB_DP': dict(tracks=[(USB_X, 43.75, 9.0, 43.75, 0.2, 0), (USB_X, 44.75, 9.0, 44.75, 0.2, 0),
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(9.0, 43.75, 9.0, 44.75, 0.2, 0)], ports=[(9.0, 44.25, (0,))]),
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'USB_DM': dict(tracks=[(USB_X, 43.25, 6.15, 43.25, 0.2, 0), (USB_X, 44.25, 6.15, 44.25, 0.2, 0),
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(6.15, 43.25, 6.15, 44.25, 0.2, 1)],
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vias=[(6.15, 43.25), (6.15, 44.25)], ports=[(6.15, 43.75, (1,))]),
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'CC1': dict(tracks=[(USB_X, 42.75, 10.675, 42.75, 0.2, 0)]),
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'CC2': dict(tracks=[(USB_X, 45.75, 10.675, 45.75, 0.2, 0)]),
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'GND': dict(tracks=[(USB_X, 40.75, 9.3, 40.75, 0.4, 0), (USB_X, 47.25, 9.3, 47.25, 0.4, 0),
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# driver VMOT ceramics (C16, C17): straight down from the socket's GND pin 7
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(22.86, 1.9, 22.86, 5.4, 0.5, 0), (43.86, 1.9, 43.86, 5.4, 0.5, 0),
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# boxed-in GND pads get their own via: U5 pin 2 (between the USB lines), C13/C14
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(11.863, 49.5, 10.55, 49.5, 0.3, 0),
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(61.775, 18.5, 61.775, 19.6, 0.3, 0), (61.775, 19.6, 61.775, 20.7, 0.3, 0)],
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vias=[(10.55, 49.5), (61.775, 19.6)],
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ports=[(9.3, 40.75, (0,)), (9.3, 47.25, (0,))]),
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# ... and from the socket's VMOT pin 8
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'+12V': dict(tracks=[(20.32, 1.9, 20.32, 5.4, 0.8, 0), (41.32, 1.9, 41.32, 5.4, 0.8, 0)]),
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'VBUS': dict(tracks=[(USB_X, 41.55, 9.3, 41.55, 0.4, 0), (USB_X, 46.45, 9.3, 46.45, 0.4, 0)],
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ports=[(9.3, 41.55, (0,)), (9.3, 46.45, (0,))]),
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}
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ORDER_FIRST = ['USB_DP', 'USB_DM', 'CC1', 'CC2', 'VBUS', 'VIN_RAW',
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# motor coils first, outermost lane first (J3.1 / J3.4 / J4.1 / J4.4), then the 12 V trunk
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'X_2B', 'X_1B', 'X_2A', 'X_1A', 'Y_1B', 'Y_2B', 'Y_1A', 'Y_2A', '+12V',
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'STAT', # short straight run under the LEDs; boxed in if left late
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'+5V_REG', '+5V', '+3V3']
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ORDER_LAST = ['GND']
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def net_order(parts):
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pads_by_net = {}
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for p in parts.values():
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for pad in p.pads():
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if pad.net:
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pads_by_net.setdefault(pad.net, []).append(pad)
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rest = [n for n in D.NETS if n not in ORDER_FIRST and n not in ORDER_LAST]
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def span(n):
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xs = [p.x for p in pads_by_net[n]]
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ys = [p.y for p in pads_by_net[n]]
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return (max(xs) - min(xs)) + (max(ys) - min(ys))
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rest.sort(key=span)
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return ORDER_FIRST + rest + ORDER_LAST, pads_by_net
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def seg_cells(x1, y1, x2, y2, L):
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n = max(1, int(math.hypot(x2 - x1, y2 - y1) / (R.G / 2)))
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out = set()
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for i in range(n + 1):
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t = i / n
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ix, iy = int(round((x1 + t * (x2 - x1)) / R.G)), int(round((y1 + t * (y2 - y1)) / R.G))
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out.add((L, ix, iy))
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return out
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def route_all(parts, order, pads_by_net, verbose=True):
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widths = set(WIDTH.values()) | set(FALLBACK) | {0.4}
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radii = {radius(w) for w in widths} | {via_radius(w) for w in widths}
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rt = R.Router(D.BOARD_W, D.BOARD_H, radii)
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rt.block_edges()
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rt.block_rect(18.75, 56.9, 67.25, D.BOARD_H) # ESP32 antenna keep-out
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for p in parts.values():
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for pad in p.pads():
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rt.add_pad(pad)
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rt.keep_vias_off_pad(pad, VIA_PAD_GAP)
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pre_components = {} # net -> list of cell sets (each one electrically connected)
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for net, pr in PREROUTE.items():
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own = rt.net_cells.setdefault(net, set())
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items = [] # (cells, endpoints)
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for (x, y) in pr.get('vias', []):
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rt.add_via(x, y, net)
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ix, iy = rt.cell(x, y)
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items.append(({(0, ix, iy), (1, ix, iy)}, {(round(x, 3), round(y, 3))}))
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for (x1, y1, x2, y2, w, L) in pr['tracks']:
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rt.add_track(x1, y1, x2, y2, w, L, net)
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items.append((seg_cells(x1, y1, x2, y2, L), {(round(x1, 3), round(y1, 3)), (round(x2, 3), round(y2, 3))}))
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# union items sharing an endpoint
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comps = []
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for cells, ends in items:
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merged = [c for c in comps if c[1] & ends]
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for c in merged:
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comps.remove(c)
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cells = cells | c[0]
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ends = ends | c[1]
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comps.append((cells, ends))
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ports = pr.get('ports')
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pc = []
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for c in comps:
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own |= c[0]
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if ports:
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pcells = set()
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for (px, py, Ls) in ports:
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ix, iy = rt.cell(px, py)
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if any((L, ix, iy) in c[0] for L in (0, 1)) or any(abs(px - e[0]) < 1e-6 and abs(py - e[1]) < 1e-6 for e in c[1]):
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for L in Ls:
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pcells.add((L, ix, iy))
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pc.append((c[0], pcells if pcells else None))
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else:
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pc.append((c[0], None))
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pre_components[net] = pc
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failures = []
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stats = {}
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t0 = time.time()
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for net in order:
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pads = pads_by_net[net]
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w0 = WIDTH[net]
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# terminals: pre-routed components (with the pads they touch) and the remaining pads
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terms = []
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used = set()
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for comp, port_cells in pre_components.get(net, []):
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cells = set(comp)
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pts = []
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for p in pads:
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pc = rt.pad_cells(p)
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if pc & comp:
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cells |= pc
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used.add(id(p))
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pts.append((p.x, p.y))
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if port_cells:
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cells = set(port_cells)
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c = next(iter(port_cells))
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pts = [(c[1] * R.G, c[2] * R.G)]
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if not pts:
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c = next(iter(comp))
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pts = [(c[1] * R.G, c[2] * R.G)]
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terms.append((cells, pts[0][0], pts[0][1], f'pre:{net}'))
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for p in pads:
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if id(p) not in used:
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terms.append((rt.pad_cells(p), p.x, p.y, f'{p.ref}.{p.num}'))
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first = min(terms, key=lambda t: (t[1] + t[2]))
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tree = set(first[0])
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remaining = [t for t in terms if t is not first]
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nseg = nvia = 0
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while remaining:
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sample = list(tree)[::max(1, len(tree) // 400)]
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def dist_to_tree(t):
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return min(abs(t[1] - c[1] * R.G) + abs(t[2] - c[2] * R.G) for c in sample)
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t = min(remaining, key=dist_to_tree)
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targets = t[0]
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remaining.remove(t)
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if targets & tree: # already connected (pads touching / overlapping)
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tree |= targets
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continue
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path = None
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tries = [w0] if net in NO_FALLBACK else [w0] + [fw for fw in FALLBACK if fw < w0]
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for w in tries:
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path = rt.search(net, radius(w), via_radius(w), tree, targets, t[1], t[2])
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if path:
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break
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if not path:
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failures.append((net, t[3]))
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continue
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a, b = rt.commit_path(net, path, w)
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nseg += a; nvia += b
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tree |= set(path) | targets
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rt.net_cells[net] |= targets
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stats[net] = (nseg, nvia)
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if verbose:
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print(f' {net:10s} pads={len(pads):2d} segs={nseg:3d} vias={nvia:2d} t={time.time() - t0:6.1f}s', flush=True)
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return rt, failures
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def stitch_vias(rt, pitch=4.0, dense=((33.0, 37.0, 53.5, 56.5, 2.0),)):
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"""GND stitching vias: one per pitch x pitch block wherever a via fits and the ground pour
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reaches it (connected) on both layers. Denser blocks under the ESP32 module."""
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import pour
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r_map = radius(0.2)
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k = rt.nid('GND')
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nx = rt.nx
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keep = {}
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for L in (0, 1):
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mask = pour.fill_mask(rt, 'GND', L, r_map, open_cells=2)
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anchors = [iy * nx + ix for (cl, ix, iy) in rt.net_cells.get('GND', ()) if cl == L]
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anchors += [rt.cell(x, y)[1] * nx + rt.cell(x, y)[0] for (x, y, n) in rt.vias if n == 'GND']
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keep[L] = pour.keep_connected(mask, nx, rt.ny, anchors)
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mv = rt.maps[via_radius(0.2)]
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gnd_vias = [(x, y) for (x, y, n) in rt.vias if n == 'GND']
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def ok(ix, iy, min_gap):
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if ix < 1 or iy < 1 or ix >= nx - 1 or iy >= rt.ny - 1:
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return False
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i = iy * nx + ix
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if rt.no_via[i] or not (keep[0][i] and keep[1][i]):
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return False
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if any(mv[L][i] not in (-1, k) for L in (0, 1)):
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return False
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x, y = rt.xy(ix, iy)
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return all(math.hypot(x - vx, y - vy) >= min_gap for vx, vy in gnd_vias)
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def blocks(x0, y0, x1, y1, p):
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s = int(round(p / R.G))
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for by in range(int(y0 / R.G), int(y1 / R.G), s):
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for bx in range(int(x0 / R.G), int(x1 / R.G), s):
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yield bx, by, s
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added = 0
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passes = [(0.0, 0.0, D.BOARD_W, D.BOARD_H, pitch)] + list(dense)
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for (x0, y0, x1, y1, p) in passes:
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for bx, by, s in blocks(x0, y0, x1, y1, p):
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cx, cy = bx + s // 2, by + s // 2
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cands = sorted(((ix, iy) for iy in range(by, by + s) for ix in range(bx, bx + s)),
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key=lambda c: (c[0] - cx) ** 2 + (c[1] - cy) ** 2)
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for ix, iy in cands:
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if ok(ix, iy, p * 0.6):
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x, y = rt.xy(ix, iy)
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rt.add_via(round(x, 3), round(y, 3), 'GND')
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gnd_vias.append((x, y))
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added += 1
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break
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print(f' stitching vias: {added}')
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return added
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def gnd_pours(rt, parts):
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"""GND copper pour on both layers, filled by pour.py (clearance 0.3 mm)."""
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import pour
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from board import uid, fmt, net_list
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from sexpr import QStr
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OX, OY = D.ORIGIN
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k = rt.nid('GND')
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r_map = radius(0.2) # 0.38 mm: 0.3 pour clearance + half cell diagonal
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net_ids = net_list()
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zones = []
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for L, lname in ((1, 'B.Cu'), (0, 'F.Cu')):
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mask = pour.fill_mask(rt, 'GND', L, r_map, open_cells=2)
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# anchors: GND copper cells on this layer (pads, tracks, vias)
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anchors = []
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for (cl, ix, iy) in rt.net_cells.get('GND', ()):
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if cl == L:
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anchors.append(iy * rt.nx + ix)
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for (x, y, n) in rt.vias:
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if n == 'GND':
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ix, iy = rt.cell(x, y)
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anchors.append(iy * rt.nx + ix)
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keep = pour.keep_connected(mask, rt.nx, rt.ny, anchors)
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polys = pour.polygons(keep, rt.nx, rt.ny)
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filled = []
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for poly in polys:
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pts = pour.to_mm(poly, R.G)
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filled.append(['filled_polygon', ['layer', QStr(lname)],
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['pts'] + [['xy', fmt(x + OX), fmt(y + OY)] for x, y in pts]])
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cells = sum(keep)
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print(f' GND pour {lname}: {len(polys)} islands, {cells * R.G * R.G:.0f} mm2')
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inset = 0.25
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outline = [(inset, inset), (D.BOARD_W - inset, inset), (D.BOARD_W - inset, D.BOARD_H - inset), (inset, D.BOARD_H - inset)]
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zones.append(['zone', ['net', str(net_ids['GND'])], ['net_name', QStr('/GND')], ['layer', QStr(lname)],
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['uuid', QStr(uid('gndzone', lname))], ['name', QStr('GND_' + lname[0])],
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['hatch', 'edge', '0.5'], ['connect_pads', 'yes', ['clearance', '0.3']],
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['min_thickness', '0.25'], ['filled_areas_thickness', 'no'],
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['fill', 'yes', ['thermal_gap', '0.5'], ['thermal_bridge_width', '0.5']],
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['polygon', ['pts'] + [['xy', fmt(x + OX), fmt(y + OY)] for x, y in outline]]] + filled)
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return zones
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def silk_labels():
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T = []
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T.append(text_node('SANDTABLE', 53.8, 27.6, 'F.SilkS', size=1.1, bold=True))
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T.append(text_node(f'CTRL v{D.VERSION}', 53.8, 29.6, 'F.SilkS', size=1.0))
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for txt, x, y, ang in (('SPIN', 4.5, 15.2, 0), ('12V', 2.4, 17.6, 0), ('USB', 2.2, 37.3, 0),
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('ARM', 71.0, 7.15, 90), ('HOME', 71.0, 21.0, 90), ('HALL', 71.4, 33.6, 90),
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('LED', 71.0, 43.2, 90), ('EXP', 74.6, 55.8, 90)):
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T.append(text_node(txt, x, y, 'F.SilkS', size=0.9, angle=ang))
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# driver orientation: match the pin names printed on the DRV8825 module
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for x1 in (38.1, 59.1): # A1 / A2 pin-1 x; pins step 2.54 mm to the left
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T.append(text_node('VMOT', x1 - 7 * 2.54, 3.5, 'F.SilkS', size=0.8))
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T.append(text_node('EN', x1 - 7 * 2.54, 13.0, 'F.SilkS', size=0.8))
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T.append(text_node('DIR', x1, 13.0, 'F.SilkS', size=0.8))
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# back side: name plate
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T.append(text_node(f'SANDTABLE CONTROLLER v{D.VERSION}', 40.0, 30.0, 'B.SilkS', size=1.6, bold=True))
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T.append(text_node('ESP32 + 2x DRV8825 | 12V in | FluidNC', 40.0, 33.0, 'B.SilkS', size=1.0))
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T.append(text_node('lazypugs 2026', 40.0, 35.5, 'B.SilkS', size=1.0))
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# JP1 (under the theta driver): bridge only for A4988 modules
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jx, jy = D.PARTS['JP1'][3], D.PARTS['JP1'][4]
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T.append(text_node('A4988 ONLY', jx, jy + 1.9, 'F.SilkS', size=0.7))
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T.append(text_node('WayWayWay', 40.0, 38.0, 'B.SilkS', size=1.0)) # PCBWay prints its order number here
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return T
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def main():
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parts = build()
|
||||
probs = check_placement(parts)
|
||||
for p in probs:
|
||||
print(' !', p)
|
||||
order, pads_by_net = net_order(parts)
|
||||
rt, failures = route_all(parts, order, pads_by_net)
|
||||
print(f'tracks={len(rt.tracks)} vias={len(rt.vias)} failures={len(failures)}')
|
||||
crowded = [(x, y, pd.ref, pd.num) for (x, y, n) in rt.vias for p in parts.values() for pd in p.pads()
|
||||
if pd.layers and pd.kind != 'np_thru_hole' and pd.dist(x, y) < R.VIA_D / 2 + VIA_PAD_GAP - 1e-6]
|
||||
print(f'vias closer than {VIA_PAD_GAP} mm to a pad: {len(crowded)}', crowded[:6])
|
||||
for f in failures:
|
||||
print(' FAILED', f)
|
||||
stitch_vias(rt)
|
||||
tracks = [(x1, y1, x2, y2, w, L, n) for (x1, y1, x2, y2, w, L, n) in rt.tracks]
|
||||
zones = [keepout_zone('ANTENNA', 18.75, 56.9, 67.25, D.BOARD_H)]
|
||||
zones += gnd_pours(rt, parts)
|
||||
os.makedirs(OUT, exist_ok=True)
|
||||
write_pcb(os.path.join(OUT, 'sandtable-controller.kicad_pcb'), parts, tracks=tracks, vias=rt.vias,
|
||||
zones=zones, texts=silk_labels())
|
||||
write_project(os.path.join(OUT, 'sandtable-controller.kicad_pro'), 'sandtable-controller')
|
||||
return failures
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
Reference in new issue
Block a user