ckochandClaude Opus 5.5
f9b4c08d60
The KiCad working copy and the Pi image work dir moved out of ~/kicad and ~/Documents into ~/Documents/projects/sandTable-local. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
220 lines
10 KiB
Python
220 lines
10 KiB
Python
"""Build the PCBWay order files and copy the KiCad project + outputs into the repo.
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Run after route.py and sch.py. Writes to ~/Documents/projects/sandTable-local/sandtable-controller/fab (outside
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the repo), then copies the results to ../ (the repo's pcb/ folder).
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"""
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import csv
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import glob
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import os
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import shutil
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import subprocess
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import sys
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import zipfile
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sys.path.insert(0, os.path.dirname(__file__))
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import design as D
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WORK = os.path.expanduser('~/Documents/projects/sandTable-local/sandtable-controller')
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NAME = 'sandtable-controller'
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PCB = os.path.join(WORK, NAME + '.kicad_pcb')
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SCH = os.path.join(WORK, NAME + '.kicad_sch')
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FAB = os.path.join(WORK, 'fab')
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GERB = os.path.join(FAB, 'gerbers')
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REPO = os.path.abspath(os.path.join(os.path.dirname(__file__), '..'))
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CLI = 'kicad.kicad-cli'
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def cli(*args):
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r = subprocess.run([CLI, *args], capture_output=True, text=True)
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if r.returncode != 0:
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sys.exit(f'kicad-cli {" ".join(args[:3])} failed:\n{r.stdout}\n{r.stderr}')
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def bom(pcb_text):
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"""PCBWay BOM straight from design.py (one line per sourcing group)."""
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parts = {r: p for r, p in D.PARTS.items() if not r.startswith(('H', 'JP'))} # holes, solder jumpers
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covered = [r for refs, *_ in D.SOURCING for r in refs]
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dup = sorted({r for r in covered if covered.count(r) > 1})
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missing = sorted(set(parts) - set(covered))
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extra = sorted(set(covered) - set(parts))
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if dup or missing or extra:
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sys.exit(f'SOURCING mismatch: duplicate {dup}, missing {missing}, unknown {extra}')
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rows = []
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for i, (refs, mfr, mpn, desc, notes) in enumerate(D.SOURCING, 1):
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fps = {parts[r][1].split(':')[1] for r in refs}
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tht = any(pcb_text.count(f'(footprint "{parts[r][1]}"') and _is_tht(pcb_text, r) for r in refs)
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qty = D.SOURCING_QTY.get(tuple(refs), len(refs))
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rows.append([i, ','.join(refs), qty, mfr, mpn, desc, ' / '.join(sorted(fps)),
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'Thru-Hole' if tht else 'SMD', notes])
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return rows
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def _is_tht(pcb_text, ref):
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# find the footprint block that carries this reference and read its (attr ...)
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key = f'(property "Reference" "{ref}"'
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i = pcb_text.find(key)
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start = pcb_text.rfind('(footprint ', 0, i)
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j = pcb_text.find('(attr ', start, i + 4000)
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return pcb_text[j:j + 30].startswith('(attr through_hole')
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def main():
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os.makedirs(GERB, exist_ok=True)
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for f in glob.glob(os.path.join(GERB, '*')):
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os.remove(f)
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# Gerbers + drill, all relative to the board's bottom-left corner
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cli('pcb', 'export', 'gerbers', '-o', GERB + '/', '-l',
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'F.Cu,B.Cu,F.Paste,F.SilkS,B.SilkS,F.Mask,B.Mask,Edge.Cuts', '--use-drill-file-origin', PCB)
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cli('pcb', 'export', 'drill', '-o', GERB + '/', '--format', 'excellon', '--excellon-units', 'mm',
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'--excellon-separate-th', '--drill-origin', 'plot', PCB)
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zpath = os.path.join(FAB, NAME + '-gerbers.zip')
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with zipfile.ZipFile(zpath, 'w', zipfile.ZIP_DEFLATED) as z:
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for f in sorted(os.listdir(GERB)):
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z.write(os.path.join(GERB, f), f)
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print('gerbers:', ', '.join(sorted(os.listdir(GERB))))
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# Centroid (pick and place)
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raw = os.path.join(FAB, 'pos-raw.csv')
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cli('pcb', 'export', 'pos', '-o', raw, '--format', 'csv', '--units', 'mm', '--side', 'both',
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'--use-drill-file-origin', PCB)
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pos = list(csv.DictReader(open(raw)))
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os.remove(raw)
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with open(os.path.join(FAB, 'centroid-pcbway.csv'), 'w', newline='') as f:
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w = csv.writer(f)
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w.writerow(['Designator', 'Mid X (mm)', 'Mid Y (mm)', 'Layer', 'Rotation', 'Value', 'Footprint'])
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for r in sorted(pos, key=lambda r: (r['Ref'][0], int(''.join(c for c in r['Ref'] if c.isdigit())))):
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w.writerow([r['Ref'], f"{float(r['PosX']):.3f}", f"{float(r['PosY']):.3f}",
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'Top' if r['Side'] == 'top' else 'Bottom', f"{float(r['Rot']) % 360:g}", r['Val'], r['Package']])
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print('centroid:', len(pos), 'parts')
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# BOM
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pcb_text = open(PCB).read()
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rows = bom(pcb_text)
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with open(os.path.join(FAB, 'bom-pcbway.csv'), 'w', newline='') as f:
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w = csv.writer(f)
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w.writerow(['Item #', 'Designator', 'Qty', 'Manufacturer', 'Mfg Part #', 'Description / Value',
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'Package / Footprint', 'Type', 'Notes'])
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w.writerows(rows)
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print('bom:', len(rows), 'lines,', sum(r[2] for r in rows), 'pieces')
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# 3D model, renders, schematic PDF
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cli('pcb', 'export', 'step', '-f', '-o', os.path.join(FAB, NAME + '.step'), '--subst-models', PCB)
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cli('pcb', 'render', '-o', os.path.join(FAB, 'render-iso.png'), '--width', '1800', '--height', '1200',
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'--quality', 'high', '--perspective', '--floor', '--rotate', '310,0,325', '--zoom', '0.9', PCB)
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for side in ('top', 'bottom'):
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cli('pcb', 'render', '-o', os.path.join(FAB, f'render-{side}.png'), '--side', side,
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'--width', '1800', '--height', '1400', '--quality', 'high', PCB)
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cli('sch', 'export', 'pdf', '-o', os.path.join(WORK, NAME + '-schematic.pdf'), SCH)
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# Assembly drawing (part outlines, references, polarity marks)
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assembly_pdf(os.path.join(FAB, 'assembly-top.pdf'))
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# Copy into the repo: KiCad project, the PCBWay order folder, renders
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kdir = os.path.join(REPO, 'kicad')
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odir = os.path.join(REPO, 'pcbway-order')
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rdir = os.path.join(REPO, 'renders')
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for d in (kdir, odir, rdir):
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os.makedirs(d, exist_ok=True)
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for f in glob.glob(os.path.join(odir, '*')):
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os.remove(f)
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for f in (NAME + '.kicad_pro', NAME + '.kicad_pcb', NAME + '.kicad_sch', 'sym-lib-table', 'fp-lib-table',
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'sandtable.kicad_sym'):
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shutil.copy2(os.path.join(WORK, f), kdir)
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tag = f'{NAME}-v{D.VERSION}'
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shutil.copy2(zpath, os.path.join(odir, f'1-gerbers-{tag}.zip'))
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shutil.copy2(os.path.join(FAB, 'bom-pcbway.csv'), os.path.join(odir, f'2-bom-{tag}.csv'))
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shutil.copy2(os.path.join(FAB, 'centroid-pcbway.csv'), os.path.join(odir, f'3-centroid-{tag}.csv'))
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shutil.copy2(os.path.join(FAB, 'assembly-top.pdf'), os.path.join(odir, f'assembly-top-v{D.VERSION}.pdf'))
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shutil.copy2(os.path.join(WORK, NAME + '-schematic.pdf'), os.path.join(odir, f'schematic-v{D.VERSION}.pdf'))
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write_order_sheet(os.path.join(odir, 'ORDER.md'), tag, rows, pcb_text)
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for f in ('render-iso.png', 'render-top.png', 'render-bottom.png'):
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shutil.copy2(os.path.join(FAB, f), rdir)
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shutil.copy2(os.path.join(FAB, NAME + '.step'), REPO)
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shutil.copy2(os.path.join(WORK, NAME + '-schematic.pdf'), REPO)
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print('order folder:', ', '.join(sorted(os.listdir(odir))))
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def assembly_pdf(out):
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"""KiCad plots on an A4 sheet with the board small in one corner: crop to the board and fit to A4."""
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full, crop = out + '.full.pdf', out + '.crop.pdf'
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cli('pcb', 'export', 'pdf', '-o', full, '--mode-single', '-l', 'F.Fab,F.SilkS,Edge.Cuts',
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'--ev', '--black-and-white', PCB)
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mm, page_h, m = 72 / 25.4, 210.0, 5.0 # A4 landscape sheet, 5 mm margin
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ox, oy = D.ORIGIN
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box = [(ox - m) * mm, (page_h - (oy + D.BOARD_H + m)) * mm, (ox + D.BOARD_W + m) * mm, (page_h - (oy - m)) * mm]
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gs = ['gs', '-q', '-sDEVICE=pdfwrite']
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subprocess.run(gs + ['-o', crop, '-c', '[/CropBox [' + ' '.join(f'{v:.1f}' for v in box) + '] /PAGES pdfmark',
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'-f', full], check=True)
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subprocess.run(gs + ['-o', out, '-dUseCropBox', '-dFIXEDMEDIA', '-dPDFFitPage',
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'-dDEVICEWIDTHPOINTS=842', '-dDEVICEHEIGHTPOINTS=595', crop], check=True)
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os.remove(full)
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os.remove(crop)
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def write_order_sheet(path, tag, rows, pcb_text):
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smd = pcb_text.count('(attr smd')
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tht_pieces = sum(r[2] for r in rows if r[7] == 'Thru-Hole')
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tht_parts = sum(len(r[1].split(',')) for r in rows if r[7] == 'Thru-Hole')
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text = f"""# PCBWay order: SandTable Controller v{D.VERSION}
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## Files
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| File | Where it goes |
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|---|---|
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| `1-gerbers-{tag}.zip` | PCB order: **Upload Gerber file** |
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| `2-bom-{tag}.csv` | Assembly order: **BOM file** |
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| `3-centroid-{tag}.csv` | Assembly order: **Centroid / pick-and-place file** |
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| `assembly-top-v{D.VERSION}.pdf` | Attach if PCBWay asks for an assembly drawing |
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| `schematic-v{D.VERSION}.pdf` | Attach if PCBWay asks for a schematic |
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## PCB settings
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| Setting | Value |
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|---|---|
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| Board type | Single pieces |
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| Size | {D.BOARD_W:g} x {D.BOARD_H:g} mm |
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| Quantity | 5 (the minimum) |
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| Layers | 2 |
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| Material | FR-4, TG130-140 |
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| Thickness | 1.6 mm |
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| Min track / spacing | 6/6 mil |
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| Min hole size | 0.3 mm |
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| Solder mask / silkscreen | any colour / white |
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| Surface finish | HASL lead-free (or ENIG) |
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| Via process | Tenting vias |
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| Finished copper | 1 oz |
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| Product No. | Specify a location (the back of the board has a "WayWayWay" marker for it) |
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## Assembly settings (PCB Assembly quote)
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| Setting | Value |
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| Service | Turnkey (PCBWay buys the parts) |
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| Assembly side | Top side only |
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| Quantity | 1 or 2 (fewer than the 5 bare boards is fine) |
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| Unique parts | {len(rows)} |
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| SMD parts | {smd} |
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| BGA / QFP parts | 0 |
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| Through-hole parts | {tht_pieces} ({tht_parts} designators; each driver socket is 2 headers) |
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| Accept alternatives | Yes, for lines marked "Any brand" |
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**Note for PCBWay** (paste into the comments box):
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> Please fit the female header sockets for A1 and A2 only. Do not supply the stepper driver modules; I will plug in my own. BOM lines marked "Any brand" may use any equivalent part to the description. U3 (AP7361C-33E) has a different pinout from AMS1117-type regulators, so please do not substitute it. Leave solder jumper JP1 open. C16 and C17 sit between the driver socket strips, under where the modules plug in; that is intended. Centroid coordinates are in mm, with the origin at the board's bottom-left corner.
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## When PCBWay sends their review
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- Check the polarity of C1, C2 (electrolytic), D1-D3, D6, D7 (diodes) and D4, D5 (LEDs) against the + and bar marks in `assembly-top-v{D.VERSION}.pdf`.
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- Check that the ESP32 (U1) antenna end sits at the board edge, over the copper-free area.
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- Check that pin 1 of U2, U3, U4 and U5 is at the dot or triangle on the silkscreen.
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- U3 is an AP7361C-33E, not an AMS1117: its pinout is different (pin 1 IN, pin 2 GND/tab, pin 3 OUT), so it must not be swapped for a 1117-type regulator.
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- JP1 is a solder jumper (bare pads), not a part: leave it open.
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"""
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with open(path, 'w') as f:
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f.write(text)
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if __name__ == '__main__':
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main()
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